MT42L256M32D4KP-3 IT:A【PDF 6/164 页】IC LPDDR2 SDRAM 8GBIT 168FBGA

您好，
买卖IC网欢迎您。
请登录
免费注册

2页 3页 4页 5页 [6页]7页 8页 9页 10页

2Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Features

List of Figures

Figure 1: 2Gb LPDDR2 Part Numbering ............................................................................................................ 3

Figure 2: Typical Self-Refresh Current vs. Temperature .................................................................................... 15

Figure 3: Single Rank, Single Channel Package Block Diagram ......................................................................... 16

Figure 4: Dual Rank, Single Channel Package Block Diagram ........................................................................... 17

Figure 5: Single Rank, Dual Channel Package Block Diagram ........................................................................... 18

Figure 6: Dual Rank, Single Channel (3 Die) Package Block Diagram ................................................................ 19

Figure 7: Dual Rank, Dual Channel Package Block Diagram ............................................................................ 20

Figure 8: Dual Rank, Dual Channel (3 Die) Package Block Diagram .................................................................. 21

Figure 9: Dual Rank, Single Channel (4 Die) Package Block Diagram ................................................................ 22

Figure 10: 134-Ball FBGA – 11mm x 11.5mm (Package Code MH) .................................................................... 23

Figure 11: 134-Ball FBGA – 11.5mm x 11.5mm (Package Code MG) .................................................................. 24

Figure 12: 168-Ball FBGA – 12mm x 12mm (Package Code KL) ......................................................................... 25

Figure 13: 168-Ball FBGA – 12mm x 12mm (Package Code KP) ......................................................................... 26

Figure 14: 168-Ball FBGA – 12mm x 12mm (Package Code LE) ......................................................................... 27

Figure 15: 216-Ball FBGA – 12mm x 12mm (Package Code KH) ........................................................................ 28

Figure 16: 216-Ball FBGA – 12mm x 12mm (Package Code KJ) ......................................................................... 29

Figure 17: 216-Ball FBGA – 12mm x 12mm (Package Code KU) ........................................................................ 30

Figure 18: 220-Ball FBGA – 14mm x 14mm (Package Code MP) ........................................................................ 31

Figure 19: 220-Ball FBGA – 14mm x 14mm (Package Code LD) ........................................................................ 32

Figure 20: 134-Ball FBGA (x16, x32) ................................................................................................................ 33

Figure 21: 168-Ball FBGA – 12mm x 12mm Single- and Dual-Die Package (SDP, DDP) ...................................... 34

Figure 22: 168-Ball FBGA – 12mm x 12mm Triple- and Quad-Die Package (3DP, QDP) ...................................... 35

Figure 23: 216-Ball 2-Channel FBGA – 12mm x 12mm ..................................................................................... 36

Figure 24: 220-Ball 2-Channel FBGA – 14mm x 14mm ..................................................................................... 37

Figure 25: Functional Block Diagram ............................................................................................................. 39

Figure 26: Voltage Ramp and Initialization Sequence ...................................................................................... 42

Figure 27: ACTIVATE Command .................................................................................................................... 54

Figure 28: t FAW Timing (8-Bank Devices) ....................................................................................................... 55

Figure 29: READ Output Timing – t DQSCK (MAX) ........................................................................................... 56

Figure 30: READ Output Timing – t DQSCK (MIN) ........................................................................................... 56

Figure 31: Burst READ – RL = 5, BL = 4, t DQSCK > t CK ..................................................................................... 57

Figure 32: Burst READ – RL = 3, BL = 8, t DQSCK < t CK ..................................................................................... 57

Figure 33: t DQSCKDL Timing ........................................................................................................................ 58

Figure 34: t DQSCKDM Timing ....................................................................................................................... 59

Figure 35: t DQSCKDS Timing ......................................................................................................................... 60

Figure 36: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 61

Figure 37: Seamless Burst READ – RL = 3, BL = 4, t CCD = 2 .............................................................................. 61

Figure 38: READ Burst Interrupt Example – RL = 3, BL = 8, t CCD = 2 ................................................................. 62

Figure 39: Data Input (WRITE) Timing ........................................................................................................... 63

Figure 40: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 63

Figure 41: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 64

Figure 42: Seamless Burst WRITE – WL = 1, BL = 4, t CCD = 2 ............................................................................ 64

Figure 43: WRITE Burst Interrupt Timing – WL = 1, BL = 8, t CCD = 2 ................................................................ 65

Figure 44: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 66

Figure 45: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 67

Figure 46: Data Mask Timing ......................................................................................................................... 67

Figure 47: Write Data Mask – Second Data Bit Masked .................................................................................... 68

Figure 48: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU( t RTP(MIN)/ t CK) = 2 ................................ 69

Figure 49: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU( t RTP(MIN)/ t CK) = 3 ................................ 70

Figure 50: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 71

PDF: 09005aef83f3f2eb

2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN

6

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2010 Micron Technology, Inc. All rights reserved.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

我的联系方式

*

*

*

相关PDF资料

MT45W1MW16BDGB-708 AT IC PSRAM 16MBIT 104MHZ 54VFBGA

MT48H32M16LFB4-75B IT:C IC SDRAM 512MB 54VFBGA

MT48H8M16LFB4-75 IT:K TR IC SDRAM 128MBIT 133MHZ 54VFBGA

MTC100-JA2-P34 CONTACT INSERT PIN

MX841BE IC CONVERTER WHITE LED 8-SOIC

MXHV9910BTR IC LED DRIVER HIGH BRIGHT 8-SOIC

MXN12FB12F MOTOR BRUSHED DC 12V 2922RPM

MXN13FB08B1 MOTOR BRUSHED DC 8V 4714RPM

相关代理商/技术参数

MT42L256M32D4KP-MS 制造商:Micron Technology Inc 功能描述:256MX32 LPDDR2 PLASTIC IND TEMP GREEN WFBGA 1.2V - Bulk